//----------------------------------------------------------------
//module name : yhz_write_back
//engineer : yhz
//date : 2021.07.28
//----------------------------------------------------------------
`include "yhz_defines.v"
module yhz_write_back (
    input  wire        i_clk             ,
    input  wire        i_rst             ,
    input  wire        i_pipeline_unlock ,
    input  wire        i_pipeline_pulse  ,
    //transfer
    input  wire        i_w_rd_en         ,
    input  wire [4:0]  i_w_rd_addr       ,
    input  wire [63:0] i_w_rd_data       ,
    //to_common_register
    output wire        o_w_rd_en         ,
    output wire [4:0]  o_w_rd_addr       ,
    output wire [63:0] o_w_rd_data        
);
//----------------------------------------------------------------
//register & wire
//----------------------------------------------------------------
    reg        pipeline_pulse ;
    reg        w_rd_en        ;
    reg [4:0]  w_rd_addr      ;
    reg [63:0] w_rd_data      ;
//----------------------------------------------------------------
//logic
//----------------------------------------------------------------
    //pipeline_pulse
    always @(posedge i_clk) begin
        if(i_rst) begin
            pipeline_pulse <= 1'b0 ;
        end
        else if(i_pipeline_unlock) begin
            pipeline_pulse <= 1'b0 ;
        end
        else begin
            pipeline_pulse <= i_pipeline_pulse ;
        end
    end
    //w_rd_en
    always @(posedge i_clk) begin
        if(i_rst) begin
            w_rd_en <= 1'b0 ;
        end
        else if(pipeline_pulse & (!i_pipeline_unlock)) begin
            w_rd_en <= w_rd_en ;
        end
        else begin
            w_rd_en <= i_w_rd_en ;
        end
    end
    //w_rd_addr
    always @(posedge i_clk) begin
        if(i_rst) begin
            w_rd_addr <= 5'd0 ;
        end
        else if(pipeline_pulse & (!i_pipeline_unlock)) begin
            w_rd_addr <= w_rd_addr ;
        end
        else begin
            w_rd_addr <= i_w_rd_addr ;
        end
    end
    //w_rd_data
    always @(posedge i_clk) begin
        if(i_rst) begin
            w_rd_data <= 64'd0 ;
        end
        else if(pipeline_pulse & (!i_pipeline_unlock)) begin
            w_rd_data <= w_rd_data ;
        end
        else begin
            w_rd_data <= i_w_rd_data ;
        end
    end
//----------------------------------------------------------------
//output
//----------------------------------------------------------------
    assign o_w_rd_en    = w_rd_en    ;
    assign o_w_rd_addr  = w_rd_addr  ;
    assign o_w_rd_data  = w_rd_data  ;
//----------------------------------------------------------------
endmodule
//----------------------------------------------------------------
